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ics9db102 idt ? t wo output dif ferential buf fer for pcie gen1 & gen2? 852 rev k 04/01/10 t wo output differential buffer for pcie gen1 & gen2 da t asheet 1 spread com pa tible pll control logic smb da t smbclk clk_int c l k _ i n c pll_bw iref pciex0 pciex1 clkreq1# clkreq0# descriptionoutput features the ics9db102 zero-delay buffer supports pci express cloc king requirements . the ics9db102 is dr iv en b y a diff erential src output pair from an ics ck410/ck505-compliant mainclock. it attenuates jitter on the input clock and has a selectable pll band width to maximize performance in systems with or without spread-spectrum clocking. 2 - 0.7v current mode diff erential output pairs (hcsl) functional bloc k dia gram ke y specifications cycle-to-cycle jitter < 35ps output-to-output sk e w < 25ps features/benefits clkreq# pin f or outputs 1 and 4/output enab le f or express card applications pll or b ypass mode/pll can dejitter incoming cloc k selectab le pll bandwidth/minimiz es jitter peaking in do wnstream pll ?s spread spectr um compatib le/tr ac ks spreading input cloc k f or lo w emi smbus interface/unused outputs can be disabled industrial temperature range available
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 2 pin configuration pll_bw 1 20 vdda clk_int 2 19 gnda clk_inc 3 18 iref **clkreq0# 4 17 **clkreq1# vdd 5 16 vdd gnd 6 15 gnd pciext0 7 14 pciext1 pciexc0 8 13 pciexc1 vdd 9 12 vdd smbdat 10 11 smbclk ics9db102 note: pins preceeded by '**' have internal 120k ohm pull down resistors 20-pin ssop & tssop vdd gnd 5,9,12,16 6,15 pci express outputs 9 6 smbus 20 19 iref 20 19 analog vdd & gnd for pll core description pin number po wer gr oups pin description pin # pin name pin type description 1 pll_bw input 3.3v input for selecting pll band width 0 = low, 1= high 2 clk_int input "true" reference clock input. 3 clk_inc input "complementary" reference clock input. 4 **clkreq0# input output enable for src/pci express output pair '0' 0 = enabled, 1 = tri-stated 5 vdd power power supply, nominal 3.3v 6 gnd power ground pin. 7 pciext0 output true clock of differential pci_expres s pair. 8 pciexc0 output complement clock of differential pci_ express pair. 9 vdd power power supply, nominal 3.3v 10 smbdat i/o data pin of smbus circuitry, 5v tolerant 11 smbclk input clock pin of smbus circuitry, 5v toler ant 12 vdd power power supply, nominal 3.3v 13 pciexc1 output complement clock of differential pci _express pair. 14 pciext1 output true clock of differential pci_expre ss pair. 15 gnd power ground pin. 16 vdd power power supply, nominal 3.3v 17 **clkreq1# input output enable for src/pci express output pair '1' 0 = enabled, 1 = tri-stated 18 iref output this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed preci sion resistor tied to ground in order to establish the appropriate curren t. 475 ohms is the standard value. 19 gnda power ground pin for the pll core. 20 vdda power 3.3v power for the pll core. pins preceeded by '**' have internal 120k ohm pull down resistors note:
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 3 absolute max symbol parameter min max units vdda 3.3v core supply voltage v dd + 0.5v v vdd 3.3v output supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v electrical characteristics - input/supply/common ou tput parameters t a = tambient; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes tambcom commercial range 0 70 c 1 tambind industrial range -40 85 c 1 input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull- up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 full active, c l = full load; 75 100 ma 1 all differential pairs tri-stated 27 50 ma 1 input frequency 3 f i v dd = 3.3 v 80 100 105 mhz 1 pin inductance 1 l pin 7 nh 1 c in logic inputs 5 pf 1 c out output pin capacitance 4.5 pf 1 clk stabilization 1,2 t stab from v dd power-up to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 spread spectrum modulation frequency f mod lexmark modulation 25 45 khz 1 pll bandwidth when pll_bw=0 400 khz 1 pll bandwidth when pll_bw=1 1.2 mhz 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v olsmbus @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup smbus sdata pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 1 guaranteed by design and characterization, not 100% tested in production. tambient pll bandwidth bw input low current input capacitance 1 operating supply current i dd3.3op
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 4 electrical characteristics - pciex 0.7v current mod e differential pair t a = tambient; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 , r p =49.9 , i ref = 475 parameter symbol conditions min typ max units notes current source output impedance zo v o = v x 3000 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max voltage vovs 1150 1,3 min voltage vuds -300 1,3 crossing voltage (abs) vcross(abs) 250 350 550 mv 1,3 crossing voltage (var) d-vcross variation of crossing over all edges 12 140 mv 1,3 long accuracy ppm see tperiod min-max values 0 ppm 1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 absolute min period tabsmin 100.00mhz nominal/spread 9 .8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 t pd pll mode. 0 150 ps 1 t pdbyp bypass mode 3.7 4.2 ns 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 output-to-output skew t sk3 v t = 50% 25 ps 1 t jcyc-cyc pll mode. measurement from differential wavefrom 35 ps 1 t jcyc-cycbyp additve jitter in bypass mode 30 ps 1 1 guaranteed by design, not 100% tested in production . . 3 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . 2 the 9db102 does not add a ppm error to the input cl ock input to output delay jitter, cycle to cycle mv measurement on single ended signal using absolute value. mv average period tperiod statistical measurement on single ended signal using
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 5 electrical characteristics - pll parameters t a = tambient; supply voltage v dd = 3.3 v +/-5% group parameter description min typ max units notes pll jitter peaking j peak-hibw (pll_bw = 1) 0 1 2.5 db 1,4 pll jitter peaking j peak-lobw (pll_bw = 0) 0 1 2 db 1,4 pll bandwidth pll hibw (pll_bw = 1) 2 2.5 3 mhz 1,5 pll bandwidth pll lobw (pll_bw = 0) 0.4 0.5 1 mhz 1,5 pcie gen 1 phase jitter (1.5 - 22 mhz) 40 108 ps 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) hi-band >1.5mhz (pll_bw=1) 2.7 3.1 ps rms 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) hi-band >1.5mhz (pll_bw=0) 2.2 3.1 ps rms 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) lo-band <1.5mhz 1.3 3 ps rms 1,2,3 notes: 1. guaranteed by design and characterization, not 1 00% tested in production. 2. see http://www.pcisig.com for complete specs 3. device driven by 932s421bglf or equivalent 4. measured as maximum pass band gain. at frequencies w ithin the loop bw, highest point of magnification is called pll jitter peaking. 5. measured at 3 db dow n or half pow er point. jitter, phase t jphasepll
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 6 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 7 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 8 general smbus serial interface inf ormation f or the ics9db102 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the wr ite address d4 (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) sends the data b yte count = x ? ics cloc k will ac kno wledg e ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics cloc k will ac kno wledg e each b yte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the wr ite address d4 (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d5 (h) ? ics cloc k will ac kno wledg e ? ics cloc k will send the data b yte count = x ? ics cloc k sends byte n + x -1 ? ics cloc k sends byte 0 thr ough b yte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controllor (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d4 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d5 (h) index block read operation slave address d4 (h) beginning byte = n ack ack
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 9 smbus table: device control register, read/write ad dress (d4/d5) pin # name control function type 0 1 pwd bit 7 sw_en enables smbus control rw functions controlled by smbus registers functions controlled by device pins 1 bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 pll bw #adjust selects pll bandwidth rw low bw high bw 1 bit 0 pll enable bypasses pll for board test rw pll bypassed (fan out mode) pll enabled (zdb mode) 1 smbus table: output enable register pin # name control function type 0 1 pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smbus table: function select register pin # name control function type 0 1 pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smbus table: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 reserved - reserved - - vendor id - - - byte 3 - revision id - - - -- - - - - -- - byte 2 reserved - -- byte 1 - -- - - - reserved - - - reserved - - reserved - byte 0 - - reserved reserved - - reserved - reserved - - reserved reserved - reserved - reserved - - reserved - reserved reserved - reserved - reserved - - reserved - reserved
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 10 smbus table: device id pin # name control function type 0 1 pwd bit 7 r 0 bit 6 r 0 bit 5 r 0 bit 4 r 0 bit 3 r 0 bit 2 r 1 bit 1 r 1 bit 0 r 0 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 0 -- - - byte 5 - writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. -- - -- - - byte 4 - - -- -- - - -- device id = 06 hex - -
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 11 min max min max a 1.35 1.75 .053 .069 a1 0.10 0.25 .004 .010 a2 -- 1.50 -- .059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 d e 5.80 6.20 .228 .244 e1 3.80 4.00 .150 .157 e l 0.40 1.27 .016 .050 n a 0 8 0 8 zd in millimeters in inches common dimensions see variations 0.635 basic 0.025 basic common dimensions 20-lead, 150 mil ssop (qsop) see variations see variations see variations see variations symbol see variations 20-pin ssop package drawing and dimensions
idt ? t wo output dif ferential buf fer for pcie gen1 & gen2 852 rev k 04/01/10 ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 12 indexarea 1 2 n d e1 e seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 de e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 20 6.40 6.60 .252 .260 10-0035 20-lead, 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 20-pin tssop p acka g e dra wing and dimensions ordering information part / order number shipping packaging package tempera ture 9db102bflf tubes 20-pin ssop 0 to +70c 9db102bflft tape and reel 20-pin ssop 0 to +70c 9db102bfilf tubes 20-pin ssop -40 to +85c 9db102bfilft tape and reel 20-pin ssop -40 to +85c 9db102bglf tubes 20-pin tssop 0 to +70c 9db102bglft tape and reel 20-pin tssop 0 to +70c 9db102bgilf tubes 20-pin tssop -40 to +85c 9db102bgilft tape and reel 20-pin tssop -40 to +85c "lf" after the package code are the pb-free configu ration and are rohs compliant. "b" is the device revision designator (will not cor relate to the datasheet revision).
ics9db102 t w o output diff erential buff er f or pcie gen1 & gen2 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. originator issue date description f 8/6/2007 1. added phase noise parameters, updated input to o utput delay values. 2. pll bw moved to pll parameters table. 3. added terminations tables. g 12/14/2007 updated general smbus interface information. h 10/29/2008 corrected "hcsl" typos. j 1/15/2010 1. added i-temp electricals 2. changed datasheet title 3. updated input frequency parameter 4. updated ordering information k rw 4/1/2010 updated ordering info for rev b

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